Authors: Assistant Professor Dr.A.Sathiya, Assistant Professor Jestadi Ramesh Babu
Abstract: The growing requirement for increased battery capacity in mobile devices like smartwatches, wireless headphones, and medical patches calls for a high level of aggressiveness with respect to power saving at both circuit and architecture levels. In this paper, we introduce a comprehensive approach that incorporates Adaptive Voltage Scaling (AVS), MTCMOS-based power gating, and Clock Gating along with an efficient power management unit (PMU) fabricated using the 65 nm CMOS technology. Our design exhibits an overall dynamic power savings of 68% when operating at a frequency of 25 MHz and a leakage power savings of 94% during sleep mode against the traditional single-Vt architecture. An SoC based simulation setup of an ECG patch is presented with active mode current consumption of 320 µA and 0.6 V and sleep mode current consumption of 45 nA.
